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PD - 91342B
Advanced Process Technology Ultra Low On-Resistance l Dynamic dv/dt Rating l 175C Operating Temperature l Fast Switching l Fully Avalanche Rated Description (R)
l l
HEXFET(R) Power MOSFET
D
IRF540NS IRF540NL
VDSS = 100V RDS(on) = 44m
Advanced HEXFET Power MOSFETs from International Rectifier utilize advanced processing techniques to achieve extremely low on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET power MOSFETs are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications.
The D2Pak is a surface mount power package capable of accommodating die sizes up to HEX-4. It provides the highest power capability and the lowest possible onresistance in any existing surface mount package. The D2Pak is suitable for high current applications because of its low internal connection resistance and can dissipate up to 2.0W in a typical surface mount application. The through-hole version (IRF540NL) is available for lowprofile applications.
G S
ID = 33A
D2 Pak IRF540NS
TO-262 IRF540NL
Absolute Maximum Ratings
Parameter
ID @ TC = 25C ID @ TC = 100C IDM PD @TC = 25C VGS IAR EAR dv/dt TJ TSTG Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current Power Dissipation Linear Derating Factor Gate-to-Source Voltage Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds Mounting torque, 6-32 or M3 srew
Max.
33 23 110 130 0.87 20 16 13 7.0 -55 to + 175 300 (1.6mm from case ) 10 lbf*in (1.1N*m)
Units
A W W/C V A mJ V/ns C
Thermal Resistance
Parameter
RJC RJA Junction-to-Case Junction-to-Ambient (PCB mount)**
Typ.
--- ---
Max.
1.15 40
Units
C/W
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1
07/01/05
IRF540NS/IRF540NL
Electrical Characteristics @ TJ = 25C (unless otherwise specified)
V(BR)DSS
V(BR)DSS/TJ
RDS(on) VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf LD LS Ciss Coss Crss EAS
Parameter Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Forward Transconductance Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Internal Drain Inductance Internal Source Inductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Single Pulse Avalanche Energy
Min. Typ. Max. Units Conditions 100 --- --- V VGS = 0V, ID = 250A --- 0.12 --- V/C Reference to 25C, I D = 1mA --- --- 44 m VGS = 10V, ID = 16A 2.0 --- 4.0 V VDS = VGS, ID = 250A 21 --- --- S VDS = 50V, ID = 16A --- --- 25 VDS = 100V, VGS = 0V A --- --- 250 VDS = 80V, VGS = 0V, TJ = 150C --- --- 100 VGS = 20V nA --- --- -100 VGS = -20V --- --- 71 ID = 16A --- --- 14 nC VDS = 80V --- --- 21 VGS = 10V, See Fig. 6 and 13 --- 11 --- VDD = 50V --- 35 --- ID = 16A ns --- 39 --- RG = 5.1 --- 35 --- VGS = 10V, See Fig. 10 D Between lead, 4.5 --- --- 6mm (0.25in.) nH G from package --- 7.5 --- and center of die contact S --- 1960 --- VGS = 0V --- 250 --- VDS = 25V --- 40 --- pF = 1.0MHz, See Fig. 5 --- 700 185 mJ IAS = 16A, L = 1.5mH
Source-Drain Ratings and Characteristics
IS
ISM
VSD trr Qrr ton Notes:
Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Forward Turn-On Time
Min. Typ. Max. Units
Conditions D MOSFET symbol 33 --- --- showing the A G integral reverse --- --- 110 S p-n junction diode. --- --- 1.2 V TJ = 25C, IS = 16A, VGS = 0V --- 115 170 ns TJ = 25C, IF = 16A --- 505 760 nC di/dt = 100A/s Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Repetitive rating; pulse width limited by
max. junction temperature. (See fig. 11) Starting TJ = 25C, L =1.5mH RG = 25, IAS = 16A. (See Figure 12) ISD 16A, di/dt 340A/s, VDD V(BR)DSS, TJ 175C Pulse width 400s; duty cycle 2%.
This is a typical value at device destruction and represents
operation outside rated limits.
This is a calculated value limited to TJ = 175C . Uses IRF540N data and test conditions.
**When mounted on 1" square PCB (FR-4 or G-10 Material). For recommended footprint and soldering techniques refer to application note #AN-994
2
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IRF540NS/IRF540NL
1000
VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V TOP
1000
I D , Drain-to-Source Current (A)
100
I D , Drain-to-Source Current (A)
100
VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V TOP
4.5V
10
10
4.5V
1 0.1
20s PULSE WIDTH TJ = 25 C
1 10 100
1 0.1
20s PULSE WIDTH TJ = 175 C
1 10 100
VDS , Drain-to-Source Voltage (V)
VDS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
3.5
RDS(on) , Drain-to-Source On Resistance (Normalized)
ID = 33A
I D , Drain-to-Source Current (A)
3.0 2.5 2.0 1.5 1.0 0.5 0.0 -60 -40 -20 0
100
TJ = 25 C
TJ = 175 C
10 4.0
V DS = 50V 20s PULSE WIDTH 5.0 6.0 7.0 8.0 9.0
VGS = 10V
20 40 60 80 100 120 140 160 180
VGS , Gate-to-Source Voltage (V)
TJ , Junction Temperature ( C)
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance Vs. Temperature
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3
IRF540NS/IRF540NL
3000
2500
VGS , Gate-to-Source Voltage (V)
VGS = 0V, f = 1MHz Ciss = Cgs + Cgd , Cds SHORTED Crss = Cgd Coss = Cds + Cgd
20
ID = 16A VDS = 80V VDS = 50V VDS = 20V
16
C, Capacitance (pF)
2000
Ciss
12
1500
8
1000
Coss
500
4
Crss
0 1 10 100
0 0 20 40
FOR TEST CIRCUIT SEE FIGURE 13
60 80
VDS , Drain-to-Source Voltage (V)
QG , Total Gate Charge (nC)
Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage
1000
1000 OPERATION IN THIS AREA LIMITED BY R DS(on)
ISD , Reverse Drain Current (A)
100
TJ = 175 C
10
ID, Drain-to-Source Current (A)
100
10
100sec 1msec
TJ = 25 C
1
1
T A = 25C T J = 175C Single Pulse 1 10 100
10msec
0.1 0.2
V GS = 0 V
0.6 1.0 1.4 1.8
0.1
VSD ,Source-to-Drain Voltage (V)
1000
VDS , Drain-toSource Voltage (V)
Fig 7. Typical Source-Drain Diode Forward Voltage
Fig 8. Maximum Safe Operating Area
4
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IRF540NS/IRF540NL
35
VDS
30
RD
VGS RG V GS
Pulse Width 1 s Duty Factor 0.1 %
D.U.T.
+
ID , Drain Current (A)
25 20 15 10 5 0
-VDD
Fig 10a. Switching Time Test Circuit
VDS 90%
25 50 75 100 125 150 175
TC , Case Temperature ( C)
Fig 9. Maximum Drain Current Vs. Case Temperature
10% VGS
td(on) tr t d(off) tf
Fig 10b. Switching Time Waveforms
10
Thermal Response (Z thJC )
1 D = 0.50 0.20 0.10 0.1 0.05 0.02 0.01 SINGLE PULSE (THERMAL RESPONSE) P DM t1 t2 Notes: 1. Duty factor D = t 1 / t 2 2. Peak TJ = P DM x Z thJC + TC 0.0001 0.001 0.01 0.1 1
0.01 0.00001
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRF540NS/IRF540NL
15V
EAS , Single Pulse Avalanche Energy (mJ)
400
VDS
L
DRIVER
300
ID 6.5A 11.3A BOTTOM 16A TOP
RG
20V
D.U.T
IAS tp
+ V - DD
A
200
0.01
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS tp
100
0
25
Starting TJ , Junction Temperature ( C)
50
75
100
125
150
175
Fig 12c. Maximum Avalanche Energy Vs. Drain Current
I AS
Fig 12b. Unclamped Inductive Waveforms
Current Regulator Same Type as D.U.T.
50K
QG
12V
.2F .3F
VGS
QGS VG QGD
VGS
3mA
D.U.T.
+ V - DS
Charge
IG
ID
Current Sampling Resistors
Fig 13a. Basic Gate Charge Waveform
Fig 13b. Gate Charge Test Circuit
6
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IRF540NS/IRF540NL
Peak Diode Recovery dv/dt Test Circuit
D.U.T*
+
+
Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer
-
+
RG VGS * dv/dt controlled by RG * ISD controlled by Duty Factor "D" * D.U.T. - Device Under Test
+ VDD
*
Reverse Polarity of D.U.T for P-Channel
Driver Gate Drive P.W. Period D=
P.W. Period
[VGS=10V ] ***
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
[VDD]
Re-Applied Voltage Inductor Curent
Body Diode
Forward Drop
Ripple 5%
[ISD ]
*** VGS = 5.0V for Logic Level and 3V Drive Devices Fig 14. For N-channel HEXFET(R) power MOSFETs
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7
IRF540NS/IRF540NL
Dimensions are shown in millimeters (inches)
D2Pak Package Outline
D2Pak Part Marking Information
UCDTADTA6IADSA$"TAXDUC GPUA8P9@A'!# 6TT@H7G@9APIAXXA!A! DIAUC@A6TT@H7GAGDI@AAGA DIU@SI6UDPI6G S@8UDAD@S GPBP 6TT@H7G GPUA8P9@ Q6SUAIVH7@S A$"T 96U@A8P9@ @6SAA2A! X@@FA! GDI@AG
25
DIU@SI6UDPI6G S@8UDAD@S GPBP 6TT@H7G GPUA8P9@ A$"T
Q6SUAIVH7@S 96U@A8P9@ QA2A9@TDBI6U@TAG@69AAAS@@ QSP9V8UAPQUDPI6G @6SAA2A! X@@FA! 6A2A6TT@H7GATDU@A8P9@
8
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IRF540NS/IRF540NL
TO-262 Package Outline
Dimensions are shown in millimeters (inches)
TO-262 Part Marking Information
@Y6HQG@) UCDTADTA6IADSG" "G GPUA8P9@A &'( 6TT@H7G@9APIAXXA (A ((& DIAUC@A6TT@H7GAGDI@AA8A Ir)AAQAAvAhriyAyvr vvAvqvphrAAGrhqArrA DIU@SI6UDPI6G S@8UDAD@S GPBP 6TT@H7G GPUA8P9@ Q6SUAIVH7@S 96U@A8P9@ @6SA&A2A ((& X@@FA ( GDI@A8
OR
DIU@SI6UDPI6G S@8UDAD@S GPBP 6TT@H7G GPUA8P9@ Q6SUAIVH7@S 96U@A8P9@ QA2A9@TDBI6U@TAG@69AS@@ QSP9V8UAPQUDPI6G @6SA&A2A ((& X@@FA ( 6A2A6TT@H7GATDU@A8P9@
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9
IRF540NS/IRF540NL
D2Pak Tape & Reel Information
TRR
1.60 (.063) 1.50 (.059) 4.10 (.161) 3.90 (.153)
1.60 (.063) 1.50 (.059) 0.368 (.0145) 0.342 (.0135)
FEED DIRECTION 1.85 (.073)
1.65 (.065)
11.60 (.457) 11.40 (.449)
15.42 (.609) 15.22 (.601)
24.30 (.957) 23.90 (.941)
TRL
10.90 (.429) 10.70 (.421) 1.75 (.069) 1.25 (.049) 16.10 (.634) 15.90 (.626) 4.72 (.136) 4.52 (.178)
FEED DIRECTION
13.50 (.532) 12.80 (.504)
27.40 (1.079) 23.90 (.941)
4
330.00 (14.173) MAX.
60.00 (2.362) MIN.
NOTES : 1. COMFORMS TO EIA-418. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION MEASURED @ HUB. 4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
26.40 (1.039) 24.40 (.961) 3
30.40 (1.197) MAX. 4
Data and specifications subject to change without notice. This product has been designed and qualified for the industrial market. Qualification Standards can be found on IR's Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.07/05
10
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